Vault protected wtih electronic time and combination lock

ABSTRACT

A vault having a door controlled by an electronic time and combination lock. Access to the vault via the door is obtained by entering two separate and independent multi-digit combination sequences at or after a specified time of day which is preset in a 24-hour clock of a specified day which is preset in a day counter. The digits of each multi-digit sequence must be entered in a predetermined order, although the digit sequences themselves may be entered in either order. Should authorized personnel possessing the multi-digit combination sequences be forced to open the vault at or after the preset time and day under threats of physical harm or the like, the vault can be opened by entry of slightly modified &#39;&#39;&#39;&#39;duress&#39;&#39;&#39;&#39; versions of the normal multi-digit combination sequences, which entries will also result in transmission of a secret alarm signal to a remote station, such as the police, alerting them to the forced entry condition. One or both of the combinations can be changed by correctly entering both combination sequences at the prescribed time and day, thereafter initiating access to the vault by, for example, retracting the bolt of the vault door, and thereafter entering the duress combination which, once accomplished, unlocks combination setting units mounted in the interior of the vault door. In lieu of using a multi-digit keyboard to enter the various digits of the combination sequences, a variable single-digit display, display stepping key, and a digit entry key are provided. Sequential entry of different digits of a combination sequence is accomplished by sequentially stepping the display to display the different digits to be entered and as each digit to be entered is displayed actuating the digit entry key. Other features are provided to accommodate various situations, such as occur when a person is inadvertently locked in the vault; an attempt is made to speed up the 24-hour clock and day counter to permit premature vault access; failure of the main power supply occurs; an attempt is made to rapidly enter different combination sequences, such as by computer means, to achieve access to the vault by trial-and-error digit entry techniques; etc.

United States Patent [1 Wagner [4 1 Apr. 15, 1975 [75] Inventor:

[ VAULT PROTECTED WTIH ELECTRONIC TIME AND COMBINATION LOCK Howard S.Wagner, Cincinnati, Ohio [73] Assignee: The Mosler Safe Company,

Hamilton, Ohio [22] Filed: Dec. 3, 1973 [21] Appl. No.: 421,267

[52] US. Cl. 340/147 MD; 340/149 A; 340/147 R [51] Int. Cl E05b 49/00[58] Field of Search 340/149 R, 149 A, 152, 340/147 MD; 235/617 B; 179/2CA, 2 DP;

[56] References Cited UNITED STATES PATENTS 3,652,795 3/1972 Wolf340/149 A Primary ExaminerHarold T. Pitts Attorney, Agent, or FirmWood,Herron & Evans [57] ABSTRACT thorized personnel possessing themulti-digit combination sequences be forced to open the vault at orafter the preset time and day under threats of physical harm or thelike, the vault can be opened by entry of slightly modified duressversions of the normal multi-digit combination sequences, which entrieswill also result in transmission of a secret alarm signal to a remotestation, such as the police, alerting them to the forced entrycondition. One or both of the combinations can be changed by correctlyentering both combination sequences at the prescribed time and day,thereafter initiating access to the vault by, for example, retractingthe bolt of the vault door, and thereafter entering the duresscombination which, once accomplished, unlocks combination setting unitsmounted in the interior of the vault door.

In lieu of using a multi-digit keyboard to enter the various digits ofthe combination sequences, a variable single-digit display, displaystepping key, and a digit entry key are provided. Sequential entry ofdifferent digits of a combination sequence is accomplished bysequentially stepping the display to display the different digits to beentered and as each digit to be entered is displayed actuating the digitentry key. Other features are provided to accommodate varioussituations, such as occur when a person is inadvertently locked in thevault; an attempt is made to speed up the 24-hour clock and day counterto permit premature vault access; failure of the main power supplyoccurs; an attempt is made to rapidly enter different combinationsequences, such as by computer means, to achieve access to the vault bytrial-and-error digit entry techniques; etc.

2 Claims, 8 Drawing Figures P,..r.TEr--HEBAPR151srs 3, 7 ,511

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VAULT PROTECTED WTlI-I ELECTRONIC TIME AND COMBINATION LOCK BACKGROUNDOF THE INVENTION This invention relates to access control and moreparticularly to a vault or the like under control of an electronic timeand combination lock.

As the sophistication of persons seeking unauthorized entry to aprotected vault increases, it has become necessary to resort to moreelaborate protective devices to avoid compromise of vault security. Avault protective system meeting present day standards against compromiseby unauthorized personnel employing sophisticated equipment andtechniques must necessarily be reasonably complex in structure andoperation. However, its design must not be such that it is undulycomplicated, rendering use by ordinary banking personnel not possessingsubstantial technical knowledge a difficult task.

It is also essential for a system, if to meet current standards ofcommercial acceptability, to accommodate reasonably foreseeableemergency situations without undue inconvenience. For example, it shouldbe possible to operate an electronic time-controlled vault at or afterthe specified time preset therein notwithstanding an intervening failureof the main electrical power supply. It should also be possible toaccess the vault without waiting for the preset time to arrive should aperson inadvertently become locked in the vault prior to the next presettime when it can be accessed. It is also important that a vaultprotective system accommodate for certain human errors, such as failureto reset the timing means prior to locking the vault to facilitateaccess at some future time and date. It is also desirable thatcombination changes be conveniently accomplished by authorized yetprotection be provided against such change by unauthorized personnel. Itis also desirable, in certain applications, to reduce the likelihoodthat unauthorized personnel observing entry of the digits of the correctcombination will be able to determine the correct combination such thatat a later time they could gain unauthorized access.

It has been an objective of this invention, therefore, to provideprotection for a vault or the like which provides a high level ofsecurity against access by unauthorized personnel, and yet is relativelysimple and convenient to use and accommodates for foreseeable mistakesby personnel using it.

SUMMARY OF THE INVENTION The foregoing has been accomplished inaccordance with certain principles of this invention by placing a vaultdoor under the control of a combination and time lock which requires, ator after a specified time of a perdetermined day preset in the system,correct entry, and in proper order, of the digits of two separatemultidigit combination sequences. In a preferred form, multiple digitkeys corresponding to the different digits of the combination sequencesare provided which, upon actuation, generate electrical signalscorresponding to the digits being entered. These signals are thenprocessed by validation means to determine if the digits entered and theorder of entry thereof for both combinations are correct. Timing meanspresettable to a predetermined time of a specified day provide anelectrical control signal which, in combination with an electricalcontrol signal produced by the validation means upon entry of bothcombinations, causes an access signal to be produced for permittingaccess to the vault. The foregoing electronic time and combination locksystem provides a high degree of protection for a vault by reason of thefact that it requires correct entry and in proper order of the digits oftwo separate and independent multi-digit combination sequences, andfurther that both such sequences be correctly entered at or after aspecified time and day preset in the system.

ln a preferred form of the invention the timing device, whichestablished the time and day when, or following which, correct entry ofthe digit combination sequences will be successful to permit access tothe vault, is an electronic clock which is advanced at a predeterminedrate in response to electrical reference pulses of fixed frequencyderived from an external power supply of fixed frequency, e.g., aconventional Hz a.c. source. Assuming the timing device is set toprovide an electrical time signal at and after 8:00 A.M. Monday morning,which signal in combination with the correct entry of both combinationsequences will permit the vault to be accessed, a person seeking tocompromise the vault protective system may attempt to accelerate theclock such that the timing signal, instead of being produced at andafter 8:00 A.M. Monday when bank employees would customarily be present,is produced the preceding Sunday when bank employees are not ordinarilypresent. Were such efforts successful, the vault could conceivably beaccessed on a Sunday by unauthorized personnel who surreptitiouslygained knowledge of the combinations without interference by bankpersonnel. Premature generation of the time signal could beaccomplished, for example, by substituting for the 60Hz power source apower supply operating at a much higher frequency. In this way, theclock timing means would be advanced at an abovenormal rate, producing atiming signal on Sunday rather than Monday. To avoid this possibilityand further enhance the security of the vault protection system, theelectronic clock timing means of this invention is provided with aninternal source of reference pulses of the desired frequency, e.g., 60Hzsignals. Should the input to the clock timing means from an externalsource be altered to substantially exceed the normal pulse rate, theinternal source responds to advance the clock at the predeterminednormal rate at which it operates. Thus, any attempt to prematurelyproduce the clock timing signal by energizing the clock with power froma source of higher frequency than normal would be ineffective.

Personnel seeking to compromise the system may also attempt to enter thecorrect combination on a trial-and-error basis, for example, by rapidlyentering in succession a vast number of combination sequences. Suchcould be accomplished with present-day technology by substituting acomputer for the conventional keyboard entry device. In this way, a vastnumber of different multi-digit combination sequences could be enteredin a methodical fashion, and in a manner of minutes, virtually assuringentry of the correct combination. To avoid the foregoing possibility andfurther enhance the security of the vault protection system, means areprovided in this invention to limit system processing of digit signalsto a rate not substantially in excess of the rate at which digits can beentered manually via a keyboard or the like. ln'a preferred form, thedigit entry rate is limited by disabling the keyboardoperated signalgenerator for a brief interval, for example, one-half second, followingentry of each digit. In this way, entry of a vast number of random digitcombinations to defeat the system on a trial-and-error basis wouldrequire weeks, if not months, and could not be accomplished on a weekendand go undetected by bank personnel.

In the event that an unauthorized person would seek to obtain access tothe vault by forcing bank personnel to enter the correct combination ator after the specifled time and day preset in the system. means areprovided whereby the system is responsive to entry of a slightlymodified form of the normal digit combination sequences herein termedthe duress sequences. Entry of the duress sequences simultaneously a)opens the vault and thereby prevents possible harm to bank personnel whootherwise might resit, and b) secretly transmits an electrical signal toa remote station, such as the police, indicating that the vault is beingopened under force, or duress, conditions.

ln accordance with a further aspect of the invention, the timing meanswhich provides the timing signal, which timing signal in combinationwith correct entry of the two-digit sequences enables the vault to beaccessed, includes a 24hour clock and a day counter. The 24-hour clockcan be preset to provide an electrical signal every 24 hours at apredetermined time, while the day counter can be preset to provide onthe day to which the counter is preset, and thereafter unless reset, anelectrical signal at the time preset in the 24-hour clock. Preferablythe date counter is preset with a count corresponding to the day onwhich the time enabling signal is desired. For example, if the daycounter is set at the close of the banking day on Friday and it isdesired that the next time enabling signal be produced on Monday, theday counter is set to a count of Upon the occurrence of each output fromthe 24-hour clock, which outputs occur at 24-hour intervals coincidentwith the time of day preset in the 24- hour clock, the day counter isdecremented. When the 24-hour clock has been decremented to a count ofzero, the time enabling signal is produced, which signal continues untilthe counter is reset to a nonzero count. An advantage of the foregoingapproach, wherein a recycling 24-hour clock is used with and todecrement a day counter, is that should bank personnel fail to reset theday counter when locking the vault at the end of the day, and insteadleave the day counter at zero, a time enabling signal will continue tobe produced until the day counter is reset to a nonzero count. Thispermits the vault to be accessed at any time prior to counter reset byentry of the proper combination notwithstanding that the day counter hasinadvertently not been set to a new day.

In accordance with a still further aspect of the invention and tofacilitate convenient entry of the combination sequences, the system isprovided with signal storage means which in effect store the fact that acombination sequence has been properly entered, which stored data is notcleared should the remaining combination fail to thereafter be correctlyentered. Thus, if one of the combinations is correctly entered and anunsuccessful attempt is thereafter made to enter the second sequence,additional attempts can be made to enter the second sequence without therequirement that the first sequence be again correctly entered.

The invention includes a further convenience feature, namely, means forenabling the independent multi-digit combination sequences to be enteredin either order. This is accomplished, in a preferred form of the 5invention, by providing two separate and individual start keysrespectively associated with each of the two independent combinationsequences. The actuation of a particular one of the start keyseffectively conditions the system for receipt and processing todetermine validity of the digits of the sequence associated with thestart key which was actuated. Depending upon the order in which thestart keys are actuated. either one of the two combination sequences canbe entered first.

To insure, once the vault has been accessed by cor' rect entry of bothmulti-digit combination sequences, that subsequent accessing of thevault cannot be accomplished without re-entry of the correctcombinations, automatic reset means are provided. In one form of theinvention, switch means are associated with the bolt which locks andunlocks the vault door and, upon retraction of the bolt to place thevault in an open condition, a reset signal is generated which, amongother things, clears the storage elements of the system which hadpreviously stored signals reflecting the fact that the correct digitsequences have been entered. Thus, once access has been initiated byretraction of the bolt following entry of the correct digit sequences,access at a later date is not possible without again entering thecorrect digits. This automatic reset scheme eliminates the possibilityof subsequent unauthorized access without re-entry of the correct digitsequences, as was possible with prior combination lock systems of themechanical dial type wherein once the proper combination wasmechanically entered via suitable dials, the vault remained unlocked andaccessible until the combination dials were turned at random, orscrambled," mechanically resetting the combination device.

In prior art multi-digit combination locks of the type whereinindividual selectively-actuable digit keys are provided corresponding toeach of the different possi ble digits which can be entered, it ispossible by observing the keyboard location of the digits actuated byauthorized personnel in entering the digits of a combina tion for anunauthorized person to determine the digits of the entered combination.To reduce this possibility of detection of the proper digits byobserving entry thereof by an authorized person, an alternative form ofkeyboard is provided in accordance with a further aspect of theinvention. Specifically, a visual display capable of displayingdifferent digits, one-at-a-time, is provided which, in combination witha digit-enter key, enables entry of the digit displayed. Since entry ofdifferent digits is accomplished by actuating a sole digitenter key, itis not possible to learn the identity of digits being entered by merelyobserving the location of the operator's finger as the keys are entered.Display of different digits such that, upon actuation of the sole digitentry key these different digits are entered, is accomplished with asecond, or advance, key which, so long as it is actuated, cycles thedisplay to successively display the different digits. When the digitwhich it is desired to enter is displayed, the advance key is releasedand the digit-enter key actuated, thereby entering the digit. Because ofthe extreme difficulty in correlating the digits being displayed withthe actuation of the advance key, it is virtually impossible todetermine the digits being entered by merely observing authorizedpersonnel actuating the advance and digit-enter keys.

In a preferred form of the invention all electrical circuit componentsof the system, including the digitentry signal generator, digitvalidator. timer, and the means responsive to the validator and timerfor permitting access to the vault upon coincidence thereof, areenergized from a conventional 60Hz a.c. main power supply. Thus, undernormal circumstances, i.e.. when the main power supply is operative. thetimer is advanced in response to a 60Hz reference signal derived fromthe main a.c. power supply. To enable the vault to be accessed at orafter the specified time and day preset in the timer notwithstanding apower failure, a stand-by battery is provided which energizes, in theevent of a main power failure, only the timer, thereby assuring that thetimer is advanced as desired. In addition to the stand-by battery,connector means are provided accessible from outside of the vault forsupplying, from an auxiliary power supply connected thereto, electricalpower to the remaining components of the system, such as the digit entrysignal generator, validator, and the circuit jointly responsive to thetimer and the validator for permitting access to the vault.

In the event of a main power failure, the timer will advance in normalfashion under energization of the stand-by battery, to produce the timeenable signal at.

the time and day preset in the timer. By connecting an auxiliary powersupply to the remaining electrical components of the system from outsidethe vault via the connector provided, the remaining circuit componentsare energized, facilitating entry of the digits of the combinationsequences, validation of the digits entered, and accessing of the vaultshould the correct digits be entered. As a consequence of this featureof the invention. should a power failure occur, for example during thecourse of a weekend when the bank is customarily closed, correctadvancement of the timing means will not be hampered, and should thepower failure still exist when the time enabling signal is produced, forexample, at 8:00 A.M. the following Monday morning, the vault cannevertheless be opened at or after the desired time by connection of theauxiliary power supply from outside the vault and correct entry of thedigits of the combination sequences.

Quite possibly, at the end of the business day and after the day counterhas been reset to a nonzero count, the vault door could be closed andlocked while a bank employee is still inside the vault. In such case itis desirable to permit the vault to be immediately re-opened by entry ofthe correct combinations without waiting for passage of the normal timeperiod ordinarily necessary for production of the time enabling signal.To accomplish this, a manually operable switch is provided within thevault which, when actuated, simulates the time enabling signal. In thisway, if, for example, a janitor sweeping out the vault and not havingknowledge of either two combination sequences, is inadvertently lockedin the vault at the close of the business day, the vault cna immediatelybe opened by having a) the janitor actuate the switch within the vaultto simulate the time enable signal and b) the bank personnel withknowledge of the combinations enter the correct digit sequences. Thus,the janitor is released without waiting until the time enable signal isproduced in normal course, such as at 8:00 A.M. the following businessday.

To facilitate convenient change of the combinations and yet restrictcombination changing to authorized personnel, a further and equallyimportant capability is incorporated in the preferred embodiment.Specifically, selectively lockable combination changing units areprovided within the vault which, even if the vault is open and access toits interior possible, are not accessible to permit changing thecombinations since they are normally locked. To change a combination. itis first necessary to enter correctly, and at or after the preset timeand day, both multi-digit combination sequences; thereafter initiateaccess to the vault by, for example, retracting the bolt. opening thedoor or the like; and finally enter the modified combination sequencecustomarily used in the duress mode. Depending upon which duresssequence is entered, access to that particular combination setting unitis provided. Since access to the vault interior following entry of thenormal digit sequences has already occurred prior to entry of the duresssequence, entry of the duress sequence as an incident to obtainingaccess to the combination changing unit is ineffective to transmit analarm signal to a remote station such as the police.

BRIEF DESCRIPTION OF THE DRAWINGS These and other advantages, featuresand objectives of the invention will become more readily apparent from adetailed description thereof taken in connection with the drawings inwhich:

FIG. 1 is a perspective view of a vault incorporating the electroniccombination and time lock of this invention;

FIG. 1A is a front elevational view of the encircled area of FIG. 1showing, in enlarged scale, the combination entry keyboard mounted inthe outside wall of the vault door;

FIG. 2 is a rear elevational view taken generally along line 2-2 of FIG.1 showing the interior of the vault door and contiguous vault wallstructure showing the bolt operating mechanism and associated controls,the digital alarm clock and associated controls, and the combinationsetting unit;

FIG. 3 is a front elevational view of an alternative form of combinationentry keyboard also useful with the electronic combination and time lockof this invention;

FIGS. 4A and 4B are schematic electrical circuit diagrams, partially inblock format, of the electrical controls incorporated in a preferredembodiment of the electronic combination and time lock of thisinvention;

FIG. 5 is a schematic circuit, in block diagram format, of the digitentry device of FIG. 3; and

FIG. 6 is a schematic circuit diagram, in block format, of a circuitsuitable for switching to an internal source of reference timing signalsto advance the 24- hour clock should an attempt be made to speed-up theclock by providing reference signals of excessively high frequency tothe 24-hour clock from an external source.

DESCRIPTION OF THE PREFERRED EMBODIMENT As shown in FIGS. 1 and 2, atypical vault 10 with which the electronic combination and time lock ofthis invention is useful includes front and rear walls 11 and 12, leftand right side walls 13 and 14, ceiling l5 and a floor 16, whichcollectively establish a protected enclosure l7 selectively accessiblevia a door 19 under control of the electronic combination and time lockof this invention. The vault 10, including the door 19, can beconstructed of conventional and known high strength materials designedto withstand forceable entry. The door 19 is mounted for pivotalswinging motion about one vertical side thereof by hinges 20. A handle21 secured to the exterior surface of the door 19 is provided tofacilitate opening and closing of the door when a bolt 22 is shifted toits retracted position shown in phantom. Bolt 22 is shiftable to itsretracted position shown in phantom in FIG. 2 in which it is disengagedfrom the door jamb 24 in response to pivoting a pivotal handle 23 alsomounted to the exterior of the door 19.

Mounted in the exterior surface of the door above handles 21 and 23 is acombination entry keyboard, shown enlarged in FIG. 1A, which facilitatesentry of the digits of the combination in a manner to be more fullyexplained hereinafter. The combination entry keyboard 25, in thepreferred embodiment depicted in FIG. 1A, includes ten selectivelyactuatable decimal digit keys 26-0, 26-1, 26-9. The digit keys 26-0,26-l, 26-9 are preferably spring-biased to an outward position in whicha pair of electrical contacts associated therewith are open-circuited orelectrically disconnected, but which upon depression, or actuation,close to electrically connect the pair of contacts associated with thedepressed key. In a preferred form, the multi-digit combination whichmust be entered as one of the conditions for operating the electroniccombination and time lock takes the form of two separate and independentmulti-digit number sequences 5,, and S,,,, each consisting of eightdecimal digits. The digits of each sequence 8,, and S,,,, as a conditionfor operating the electronic combination and time lock, must be enteredin a predetermined digit sequence, although either sequence 5,, or S,,,may be entered first.

To facilitate entry of the digits of each of the two multi-digitcombination sequences S, and S,,, in either of the two possiblechronological orders, i.e., combination sequence 5,, followed bysequence S,,, or vice versa, a start S, key 28 and a start S,,, key 29are provided. Start 5,, and S,,, keys 28 and 29 are actuated prior toentering the multi-digit combination sequences 3,, and S,,,,respectively, via the digit keys 26-0, 26-1, 26-9. While the start 5,,key 28 and the start S,,, key 29 must be actuated before entry of thedigits of their respectively associated multi-digit combination sequence8,, and S,,,, respectively, either sequence S, or S,,,, and hence eitherstart key 28 or 29, may be actuated first. To indicate proper entry inthe correct sequence of the digits of each multi-digit combinationsequence 8,, and S,,,, which preferably have eight digits per sequence,a correct 5,, indicator light 30 and a correct S,,, indicator light 31are provided. These lights 30 and 31 become illuminated upon correctentry in the proper sequence of the digits of their respectivelyassociated multi-digit combination sequence S,, and S,,,.

As shown best in FIG. 2, which is an elevational view of the rearinterior surface of the vault door 19, the bolt 22 is seen to take theform of an elongated rod which is mounted for horizontal sliding motionbetween lock and unlock positions by bracket 32 secured to the rearsurface of the door. In the extended or lock position of bolt 22 (shownin solid lines) the free end 33 of the bolt projects into anappropriately located recess 34 formed in the door jamb 24 preventingopening of the door; while in the retracted or unlock position (shown inphantom) the outer end 33 of the bolt is disengaged from the door jambrecess 34, permitting the door to be opened.

To facilitate horizontal sliding motion of the bolt 22 between its lockand unlock positions upon correct entry of both combination sequences5,, and S,,,, the pivotal handle 23 mounted at the front of the door 19is provided. The handle 23 is fixed at one end to a hori' zontalactuating shaft 36 which extends through the door 19, the other end ofthe shaft being fixed to the lower end of a lever 37 located adjacentthe inner surface of the door. The lever 37 has its other end pinned tothe inner end 39 of the bolt. When the handle 23 is pivotedcounterclockwise, as viewed in FIG. 2, the shaft 36 and lever 37 whichare rigidly secured to each other rotate about the axis of the shaft 36in a counterclockwise direction shifting the bolt 22 from the extended,lock position (shown in solid lines) to the retracted, unlock position(shown in phantom lines). When the handle 23 is rotated in the clockwisedirec' tion, as viewed in FIG. 2, the shaft 36 and lever 37 operate toshift the bolt 22 from its retracted, unlock posi tion to its extended,lock position in which its outer end 33 engages the door jamb 24.

To alternatively permit and prevent, on a selective basis, horizontalshifting motion of the bolt 22 between its lock and unlock positions, anotch 40 in the upper surface of the bolt 22 is provided in combinationwith a selectively operable vertically shiftable detent 42. The detent42 is mounted by suitable brackets 43 secured to the interior of door 19for vertical sliding motion between a lower position in which the bottomfree end thereof engages the bolt notch 40 to prevent movement of thebolt from the lock position, and an upper position in which the lowerend of the detent 42 is disengaged from the bolt notch 40 to facilitatemovement of the bolt between the lock and unlock positions. A pair ofsolenoids 44A and 44B mounted to the interior of door 19 have verticallyshiftable cores 45A and 45B connected at their lower ends to oppositeends of a horizontal bar 46, the midportion of which is secured to theupper end of the detent 42. Solenoids 44A and 44B are selectivelyenergizable to raise the detent 42 from its lower position engaging thenotch 40 of the bolt 22 to an upper position disengaged from the boltnotch to permit the bolt 22 to be moved from its lock position to itsunlock position by the handle 23. Energization of solenoids 44A and 44Bto permit unlocking of the vault door 19 occurs, in a manner to bedescribed, when both combination sequences 5,, and S,,, have beenproperly entered during a specified time period of a specified dayestablished by the setting of a digital alarm clock, in a manner also tobe described in detail hereinafter.

Mounted to the interior of the door 19 is a control panel for settingthe digital alarm clock, which includes a 24-hour clock and a daycounter, to the correct time of day, and for setting the specified dayand period during such day, when the digital alarm clock will provide anoutput which, in combination with correct entry of the digit sequences8,, and S,,, will enable the bolt 22 to be moved from its lock to itsunlock position via handle 23 to open the vault. Also mounted on therear surface of the door 19 is a digital read-out, or display 52, whichdisplays in digital format, and on an alternative basis, either a) thecorrect time of day in hours, minutes and seconds, or b) the specifiedtime period during the clay preset in the 24-hour clock when2-6-5-4-9-8-6-0, the duress sequence 5,,,

the 24-hour clock provides a signal which, in combination with a similarsignal from the day counter correlated to a specified day presettherein, facilitates opening the vault upon proper entry of both thedigit sequences 5,, and S,,,. A second display or digital read-out 53 ismounted on the rear surface of the door 19 for providing a digitalread-out of the number of days from the setting of the day counter whichmust elapse before the signal from the 24-hour clock is effective toenable the vault to be opened upon correct entry of both combinationsequences 5,, and S,,,. Switches 51 permit setting the day counter and24-hour clock to the desired settings in a manner to be described.

For example, if at the end of the business day on Friday, it is desiredto have the digital alarm clock produce a signal at 8:00 A.M. thefollowing Monday to permit opening of the vault door (assuming thecorrect number sequences 5,, and 5,,, are entered at that time), the24-hour clock will be set for 8:00 A.M. and the day counter set for 3days hence, i.e., Monday morning. Since the door unlock enabling timesignal is to be provided at 8:00 A.M. on the third day, i.e., Mondayfollowing the day on which the digital alarm clock is set, i.e., Friday,the digital display 53 of the 24-hour clock will display either thecorrect time of day such as 5:00 P.M. when the digital alarm clock isbeing reset for Monday at 8:00 A.M., or the time of day when the 24-hour clock is to produce its output signal, namely, at 8:00 A.M. andthereafter. Instead of using the same display 52 to alternativelydisplay the correct time of day and the time of day when the unlockingof the vault is to be permitted by proper entry of the number sequences5,, and 5,,, two separate displays could be provided.

As indicated the vault door 19 is capable of being unlocked upon properentry, following passage of the time interval established by the digitalalarm clock, of both multi-digit number sequences 5,, and S,,,.Additionally, the vault door is capable of being unlocked if, followingpassage ofthe time interval established by the digital alarm clock,digit sequences 5,, and 5,,, are both entered, these latter digitsequences being hereafter referred to as duress sequences. In order toavoid possible harm to bank employees having knowledge of the digitsequences 5,, and 5,,,, who may be coerced or threatened by a personintent on gaining unlawful access to the vault, it is desirable toprovide means whereby the bank employee can simultaneously unlock thevault and secretly transmit an electrical signal to a remote station,such as to the police, indicating that the bank is being openedforceably and under duress.

Accordingly, in addition to enabling the vault 10 to be unlocked byentry of the normal digit sequences 5,, and 5,,, during the time periodand day established by the digit alarm clock, in which case no remotepolice alarm is transmitted, it is also possible to open the vault at orafter the time and day determined by the digital alarm clock as well assimultaneously transmit an alarm to a police station or the like, byentering duress digit sequences 5,, and 5,,,. Digit sequence 5,, differsfrom digit sequence 5,, in accordance with a preferred form of theinvention, in that only the last digit of the sequence is altered. Forexample, if the normal sequence 5,, is 5-2-3-9-4-7-6-3, the duresssequence 5,, will, in a preferred form, be 5-2-3-9-4-7-6-0, the lastdigit only being changed. Similarly, if the normal sequence 5,,, is willbe 10 2-6-5-4-9-8-6-8, with the last digit only being changed.

To facilitate changing the combination sequences 5,, (and 5,,) and/or5,,, (and S,,,'), combination setting units 56 and 58, respectively, areprovided. Each of the combination setting units 56 and 58 includes apatch board 56A and 58A, respectively. Each patch board 56A and 58Aincludes a row of digit sockets 56C and 58C, respectively, and a row ofsequence sockets 56D and 58D, respectively. Depending upon theconnections made by jumper cables or the like between the sequencesockets 56D and 58D and the respectively associated digit sockets 56Cand 58C, the multi-digit combination sequences 5,, (and 5,,) and 5,,,(and 5m). respectively, will vary. For example, if the normal digitsequence 5,, is 5-2-3-9-4-7-6-3 (5,, being 5-2-3-9-4-7-6-0), jumpercables would be connected between sockets l and 5, 2 and 3, 3 and 3, 4and 9, 5 and 4, 6 and 7, 7 and 6, and 8 and 3 of socket sets 56C and56D, respectively, of patch panel 56A of the combination setting unit56. Similarly, if the combination normal sequence 5,,, is2-6-5-4-9-8-6-0 (S,,,' being 2-6-5-4-9-8-6-8), interconnection withjumper cables of sockets 2 and 9, 6 and 10, 5 and 11, 4 and 12, 9 and13, 8 and 14, 6 and 15, and 0 and 16 of socket sets 58C and 58D,respectively, of patch panel 58A of combination setting unit 58 would bemade.

Each of the combination setting units 56 and 58 includes a closure ordoor 56E and 58E, respectively, which in their closed positions denyaccess to the combination setting sockets and jumper cables, and whichin their open position permit such access for changing the numbersequences 5,, and S,,,. Solenoids 56F and 58F have vertically shiftablecores 566 and 586 engageable in their lowermost position with aperturedears 56H and 581-1 mounted to the inner surface of doors 56E and 58E toselectively lock and unlock the doors 56E and 58E.

In order to gain access to one or both of these combination settingpatch panels 56A and 58A to change one or both of the combinationsequences 5,, (and 5,,) and 5,,, (and S,,,') it is necessary that bothdigit sequences 5,, (or 5,,) and 5,, (or S,,,') be entered at or afterthe time and day established by the digital alarm clock and the bolt 22retracted, whereupon the vault door can be opened to permit access tothe rear of the vault door, and thereafter that the duress sequence 5,,and/or 5,,, be correctly entered whereupon solenoids 56F and/or 58F areenergized to unlock doors 56E and/or 58E, depending upon whether one orthe other or both of the multi-digit number sequences 5,, (and also 5,,)and 5,,, (and also S,,,') are to be changed. If only combinationsequence 5,, (and 5,,) is to be changed, it is necessary that both digitsequences 5,, (or 5,,) and 5,,, (or S,,,') be entered at or after thespecified time and day established by the digital alarm clock, the bolt22 thereafter placed in its unlock position to provide access to therear of vault door 19, and that the duress sequence 5,, be entered toenergize solenoid 56F to unlock door 56E. Similarly, if only sequence5,,, (and S,,,') is to be changed, it is necessary that both sequences5,, (or 5,,) and 5,,, (or S,,,') be entered at or after the time and dayestablished by the digital alarm clock, that the bolt 22 be placed inits retracted position to facilitate access to the rear of the vaultdoor, and thereafter that the duress sequence 5,, be entered to energizethe solenoid 58F to unlock door 58E. If both digit sequences 5,, (and5,,) and 5,,, (and S,,,') are to be changed, it is essential that digitsequences 5,, (or S,.') and S,,, (or S,,,) be entered at or after thetime and day established by the digital alarm clock, that the bolt 22 beplaced in its unlock position to facilitate access to the rear of vaultdoor 19, and that thereafter both duress sequences 5,, and 5," beentered to energize solenoids 56F and 58F to unlock doors 56E and 58E,respectively.

Mounted to the rear surface of the door 19 and associated with thehorizontally shiftable bolt 22 are stationary electrical contacts 60, 61and 62 which cooperate with a movable electrical contact 63 secured tothe upper surface of the bolt via an electrically insulative bracket 64,and stationary contacts 65, 66 and 67 which cooperate with a movableelectrical contact 68 secured to the lower surface of the bolt via aninsulative bracket 69. When the bolt 22 is in the extended lockposition, electrically conductive contact 63 connects stationarycontacts 61 and 62 such that should a duress signal be present on line70, as a consequence of entry when the door is closed of both duresssequences 8,, and S,,, during the time interval and day established bythe digital alarm clock, indicating that a duress condition exists, theduress signal on line 70 will be connected to output line 71 to a policestation or the like. Additionally, when the bolt 22 is in the extendedlock position, contacts 66 and 67 are electrically connected byelectrically conductive contact 68 to charge a capacitor 72 from asource of positive potential 73. When the bolt 22 is thereafterretracted and stationary contacts 65 and 66 connected via the contact 68which has not shifted leftwardly, the capacitor 72 will discharge via aline 74 to reset the electronic lock circuitry. Resetting is effectiveto de-energize solenoids 44A and 44B enabling the detent 42 to dropvertically such that when the bolt 22 is once again moved to itsextended position following opening of the door, the detent 42 and boltnotch 40 will automatically engage to lock the bolt in its extendedposition. Resetting is also effective to require that both digitsequences S (or S,,) and S,,, (or S,,,) again be entered during the timeand day specified by the electronic alarm clock to facilitate access tothe vault once the door has been closed and the bolt placed in itsextended position wherein it is automatically locked by the detent 42 inthe manner described.

When the bolt 22 is in its retracted, unlock position, stationarycontacts 60 and 61 are electrically connected by the electricallyconductive contact 63. The effect of this is to apply a duress signalappearing on line 70, produced by entry of one or both duress sequencesS,, or S,,, when the door is open and it is desired to change one ormore of the sequences 5,, (and S,,) or S,,, (and S,,,) to line 75 of acombination setting access circuit, to be described, which in a mannerdescribed previously permits doors 5615 and/or 58E to be openeddepending upon whether one or both of the patch boards 56A and 58A is tobe accessed to permit changing of the combination sequences 8,, (and Sand S,,, (and S,,,).

Assuming that the combination lock circuitry has been reset by return ofthe bolt 22 to its extended lock position and that the electronic alarmclock has been set via the control panel 50 to provide an enablingsignal at and after a specified time during some future day, such as ator after 9:00 A.M. the day following setting of the day counter of thedigital alarm clock, the sequence of operations involved in unlockingthe vault door will now be briefly summarized. Specifically, at 9:00A.M. the day following setting of the day counter, each of themulti-digit combination sequences 5.. (or S,,') and S,,, (or S,,,) areentered via the combination entry keyboard 25. if digit sequence 5,, (0rn is to be entered first, the start 5,, key 28 is depressed, whereuponthe digit keys of sequence 5,, (Or 5 are sequentially momentarilydepressed. For example, if digit sequence S,, is 5-2-3-9-4-7-6-3, digitkeys 26-5, 26-2, 26-3, 26-9, 26-4, 26-7, 26-6 and 26-3 are sequentiallymomentarily actuated. Upon conclusion of this, lamp 30 becomesilluminated indicating that digit sequence S, was correctly entered.Following correct entry of sequence S, (or S,,) digit sequence S,,, (orS,,,) is entered. This is accomplished by first momentarily depressingthe start S key 29, followed by sequential entry of the digit keyscorresponding to sequence 5,, (or S,,,). If the digits of sequence S,,,are 2-6-5-4-9-8-6-0, digit keys 26-2, 26-6, 26-5, 26-4, 26-9, 26-8, 26-6and 26-0 are sequentially entered, whereupon lamp 31 becomes illuminatedto indicate that sequence S,,, has been correctly entered.

With both of the normal digit sequences S,, and S,, both correctlyentered and such entry having taken place at or after the time and dayset in the digital alarm clock, in this example, 9:00 A.M. of the dayfollowing setting of the day counter, the solenoids 44A and 44B areenergized to retract their armatures 45A and 45B and in turn disengagethe detent 42 from the bolt notch 40. With detent 42 and bolt notch 40disengaged, the bolt 22 can be horizontally shifted by rotation ofhandle 23 in a counterclockwise direction as viewed in FIG. 2 to theretracted position shown in phantom lines, disengaging bolt end 33 fromjamb recess 34. The door can now be opened by pulling handle 21outwardly.

Movement of the bolt 22 from the extended lock position to the retractedunlock position shifts movable electrical contact 68 to connectstationary contact 65 and 66 enabling capacitor 72, now fully charged,to discharge via line 74 to a reset circuit. As a consequence, theelectronic combination lock circuitry is reset to deenergize solenoids44A and 4413, allowing detent 42 to drop atop the bolt between the notch22 and the bolt end 33. When the door is later closed and the bolt 22returned to its extended lock position, the detent 42 will automaticallyseat in the bolt notch 40 to prevent retraction of the bolt until thenext successful entry of combination sequences 5,, and S,,, at the timeand day prescribed by the electronic alarm clock. The discharge ofcapacitor 72 on line 74 to the reset circuit is also effective todestroy the circuit conditions of the electronic combination lockpreviously existing as a consequence of the correct entry of sequencesS, and S,,, at or after the time and day set by the electronic alarmclock. It is now necessary to again enter the correct combinationsequences S, and S,,, at or after the time and day prescribed by theeldctronic alarm clock before the solenoids 44A and 44B can again beenergized to permit the bolt 22 to be retracted from a locked to anunlocked position.

While the foregoing examples assumed that digit sequence S was enteredprior to digit sequence S,,,, unlocking of the vault can be accomplishedby entry of digit sequence S,,, followed by correct entry of digitsequence S,,, providing that start S key 29 is actuated prior to entryof digit sequence 8,, and further that start S key 28 is actuated priorto entry of digit sequence S,,,

with the digit sequences and their respective start keys being actuatedin the order of sequence S,,, first and sequence S, thereafter.

Further, had duress conditions existed, the vault door could have beenunlocked at or after the time and day set by the electronic alarm clock,for example, at or after 9:00 A.M. the following day by setting of theday counter, by entry, in any order, of the duress sequences 5,, andS,,,. In addition to unlocking the vault door, entry of the digitsequences 5,, and S,,, during the time interval and day set in theelectronic clock would have been effective to generate an electricalsignal on line 70 which would have been transmitted to the policestation on line 71 by contact 63 which, until both duress sequences 8,,and S,,, are correctly entered and the bolt 22 shifted to its retractedposition, is in its lock position bridging stationary contacts 61 and62.

With reference to FlGS. 4A and 4B, the keyboard 26 includes ten digitkeys 26-0, 26-1, 26-9. Each digit key is normally open such that alogical l is present on each of the digit key output lines which areinput to a comparator 100. The logical l signals are provided by aS-volt potential source 26A connected to the digit key output lines viaa resistor 26B. The connection to source 26A via resistor 26B is shownonly for keys 26-0 and 26-8, although all digit keys 26-0 through 26-9are so connected. Source 26A is supplied from power sup ply 201 to bedescribed. Momentary actuation of any one of the digit keys 26-0, 26-1,26-9 connects the output line of the actuated digit key to groundpotential 26C with the result that current flows through the associatedresistor 26B to ground from the source of positive potential 26A,applying a voltage slightly above ground potential, or a logical signal,to the output of the digit key actuated. Release of the momentarilyactuated digit key restores the output of that key to a logical 1 levelsince current through associated resistor 26B, and the resulting voltagedrip thereacross, decreases to zero when the digit key is released.

Start S key 28 and start S,,, key 29 operate in the same manner as thedigit keys 26-0, 26-1, 26-9 to provide a logical 0 signal on theiroutput lines when their respective output keys are momentarily actuatedto a closed-circuit condition, and provide a logical 1 signal level ontheir respective output lines when in the unactuated, open-circuitcondition. Isolating diodes 26D, 26D are connected in the output linesof digit keys 26-0 and 26-8, which particular keys are the duress keysfor digit sequences S, and S,,,, respectively, between the respectivedigit key and the resistor 26B for reasons to become apparent hereafterin connection with the duress capability.

The comparator 100 includes ten Exclusive-Or circuits 100-0, 100-1,100-9 associated respectively with the ten digits 0, 1, 9 represented bydigit keys 26-0, 26-1, 26-9. Each of the Exclusive-Or gates of thecomparator 100 has one of its two inputs connected to a respectivelyassociated different digit key, and the other of its inputs connectedvia a respectively associated different inverter to a respectivelyassociated different output of a correct combination number sequencegenerator 110. During entry of a digit sequence 8,, or S,,,, if thedigit is a correct digit and is being entered in proper order, a logical0 level is input to the Exclusive-Or circuit associated with the correctdigit from the correct digit key while a logical l is input to theExclusive-Or circuit associated withthe correct digit, followinginversion, from the correct combination number sequence generator 110.For example, if sequence 8,, is 5-2-3-9-4-7-6-3 and the second digit 2thereof is being entered, Exclusive-Or gate -2 will have a logical 0input to it from actuated digit key 26-2 and a logical 1 input to it asa consequence of a logical 0 being provided by the correct combinationnumber sequence generator which is then inverted prior to input to theother terminal of Exclusive-Or gate 100-2. Thus, when the correct digitof a sequence 8,, or S,,, is entered in proper order, the Exclusive-Orgate associated with that digit will provide on its output line alogical 1 signal.

lf digit key 26-2 corresponding to the digit 2 is not actuated as thesecond digit of the illustrative sequence S,,, a logical 1 will be inputto Exclusive-Or gate 100-2 from digit key 26-2. Since a logical l isinput to the other terminal of Exclusive-Or gate 100-2 as a consequenceof the logical 0 input to its associated inverter circuit from thecorrect combination sequence generator 110, a logical 0 will be providedat the output of Exclusive-Or gate 100-2. This logical 0 output fromExclusive-Or gate 100-2, in a manner to be apparent hereafter, will besensed by an incorrect digit detector circuit 112.

Again assuming the correct second digit of sequence S, is a digit 2, ifduring entry of the second digit a digit key other than the correct key26-2 is actuated, such as digit key 26-3, a logical 0 signal will beprovided on the output of Exclusive-Or gate 103 which, in a manner to bedescribed hereafter, will be detected by the incorrect digit detectorcircuit 112.

Specifically, if digit key 26-3 corresponding to an incorrect digit isdepressed instead of digit key 26-2, a logical 0 is input from depresseddigit key 26-3 to one terminal of the Exclusive-Or gate 100-3, while alogical 0 is input to the other terminal of the Exclusive-Or gate as aconsequence of inversion of a logical 1 signal provided by the correctcombination of the sequence generator 110. With a logical 0 signal inputto both terminals of Exclusive-Or gate 100-3, a logical O is provided atthe output of the Exclusive-Or gate which, as noted, is detected by theincorrect digit detector circuit 112.

Similarly, if digit key 26-3 corresponding to an incorrect digit isactuated simultaneously with digit key 26-2 corresponding to a correctdigit, a logical 0 will be produced from Exclusive-Or gate 100-3 whichwill be detected by incorrect digit circuit 112 notwithstanding that alogical 1 signal is produced by Exclusive-Or gate 100-2 reflecting thefact that the correct digit key 26-2 was actuated.

If during actuation of digit key 26-2, a correct key, none of the digitkeys are actuated, logical l signals will be provided from theExclusive-Or gate 26-0, 26-1 and 26-3 through 26-9 reflecting the factthat no incorrect digit was entered. For example, assuming digit key26-3, an incorrect digit, is not actuated, a logical l is input fromthis unactuated digit key to its respectively associated Exclusive-Orgate 100-3, while a logical 0 input to the other terminal of thisExclusive-Or gate as a consequence of inversion of a logical 1 signalprovided by the correct combination number sequence generator 110,producing a logical 1 signal from the Exclusive-Or gate reflecting thefact that digit key 26-3, corresponding to an incorrect digit, was notactuated.

Summarizing, if during the entry of a digit of one of the digitsequences S, or S,,, the key corresponding to the correct digit and onlythat key is actuated, logical l signals will be provided at the outputsof all the Exclusive-Or gates 100-0, 100-1 100-9. If an incorrect key isactuated, either alone or simultaneously with actuation of the correctdigit key, a logical will be output from the Exclusive-Or gateassociated with the incorrectly actuated key, which logical 0 signalwill be detected by the incorrect digit detector circuit 112, in amanner to be described. Thus, the circuit of this invention operates todetect actuation of a correct digit key in proper sequence, as well asactuation of an incorrect digit key. An incorrect" digit key may be akey corresponding to a digit which is not contained in the correct digitsequence, such as the digit 1 in a sequence 5,, having digits5-2-3-9-4-7-6-3, or may be a key corresponding to a digit which isincluded in the digit sequence, but which actuation occurs out ofsequence or order, such as occurs if digit key 26-2 corresponding to a 2is actuated other than as the second digit of the sequence 5,,comprising digits 5-2-3-9-4-7-6-3.

The correct combination sequence generator 110 provides logical Osignals to the inverters associated with the Exclusive-Or gates 100-0,100-1, 100-9 of the correct digits. The Exclusive-Or gates 100-0, 100-1,100-9 associated with the correct digits of a digit sequence 5,, or S,,,receive their respective signals from the correct combination numbersequence generator 110 on a sequential basis corresponding to theposition in the sequence 5,, or S,,, of the respective digits with whichthe Exclusive-Or gates are associated. Thus, if digit sequence S,, isbeing entered into the keyboard 26, the correct combination numbersequence generator 110 successively provides logical 0 signals to theinverters associated with digits 5-2-3-9-4-7-6-3, that is, toExclusive-Or gates 100-5, 100-2, 100-3, 100-9, 100-4, lOO-7, l00-6, and100-3.

To accomplish the foregoing, a key pulsing circuit 115 is provided. Thiscircuit includes two NAND-gates 116 and 117 whose individual inputs areconnected to different ones of the outputs of the digit keys 26-0, 26-l,26-9, and a NOR-gate 118 connected to the outputs of NAND-gates 116 and117. The key pulsing circuit 115 provides on its output line 119 alogical 0 pulse each time one or more of the digit keys 26-0, 26-1, 26-9is actuated. Output line 119 is input via an Exclusive-Or gate 120 to arapid entry prevention circuit 121. Rapid entry prevention circuit 121limits the processing of signals by the circuit of FIGS. 4A and 4B to arate corresponding to that which occurs when digits are entered manuallyvia the keyboard 26. This eliminates the possibility that, for example,someone attempting to unlawfully compromise the system would, instead ofmanually actuating the digit keys 26-0, 26-1, 26-9 a multiplicity ofdifferent times in attempting to produce the correct combinationsequence by trial and error, would instead connect a computer to thecomparator 100 and in a few minutes simulate the entry of a very largenumber of different digit sequences in an effort to accelerate entry ofthe correct combination by trial and error methods.

Rapid entry prevention circuit 121 includes a single shot, or monostablemultivibrator, circuit 122 responsive to the output of Exclusive-Or gate120. Single shot 121 switches on the leading edge of the logical 1signal output from Exclusive-Or gate 120 each time a digit key 26-0,26-1, 26-9 is actuated. Also included is a one shot circuit 123 whichtriggers on the trailing edge of a logical 1 output from theExclusive-Or gate each time a digit key is depressed. The output of oneshot 123 is input on line 124 to one shot 122 preventing re-triggeringof one shot 122 for the duration of the output pulse provided by oneshot 123. A third one shot circuit 125 is responsive to the output ofone shot circuit 122 and triggers on the rising edge of the logical lpulse provided by one shot 122. One shot 125 provides complementarypositive (l and negative (0) pulses on lines 126 and 127 for theinterval established by one-shot 125. The periods of one shots 122, 123and 125 are 18, 22, and 7 milliseconds, respectively.

The logical 0 or negative pulse on line 127 from one shot 125 of therapid entry prevention circuit 121 is input to a binary counter 130.Thus, each time a digit key 26-0, 26-1, 26-9 is actuated an input isprovided to binary counter 130 on line 127. Binary counter 130 also isresponsive to a signel on line 132 produced as a consequence ofmomentarily actuating the start 5,, key 28 and a signal on line 133produced as a consequence of momentarily actuating the start S,,, key29.

The input on line 132 to the binary counter 130 is produced by applyingthe output of start 5,, switch 28 to line 127 via a NOR-gate and aninverter 141 which in combination constitute a logical OR-gate.Similarly, the input on line 133 to the binary counter 130 is producedby applying the output of start S,,, switch 29 to line 133 via a NORcircuit 142 and an inverter 143 which collectively constitute a logicalOR circuit.

If the start 5,, key 28 has been actuated producing an input to counter130 on line 132, as the counter is thereafter successively pulsed online 127 coincident with the successive actuation of the digit keys26-0, 26-l, 26-9, the counter will provide on its output lines 131, inbinary format, signals corresponding to successive counts of 1, 2, 3, 4,5, 6, 7 and 8. Similarly, if the binary counter 130 is input with asignal on line 133 as a consequence of actuating the start S,,, key 29,when the counter 130 is thereafter successively pulsed on line 127 as aconsequence of successive actuation of the digit keys, the counter 130will provide on its output lines 131 signals in binary format correlatedsuccessively to counts of 9, 10, 11, 12, 13, 14, 15 and 16.

The successive outputs on counter output lines 131 corresponding tosuccessive counts of l, 2, 3, 4, 5, 6, 7, and 8, if the start 5,, key 28is depressed, or counts of 9, 10, ll, 12, 13, 14, 15 and 16 if the startS,,, key 29 is depressed, are input to a binary-to-hexadecimal converter137 having 16 output lines 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11,12,13,14,15, and 16. Output lines 1, 2, 3, 4, 5, 6, 7 and 8, preferably in theform of patch board sockets, correspond to sockets 56D of combinationsetting unit 56 for setting the digits of combination sequence S,,,while output sockets 9, 10, 11, 12, 13, 14, 15 and 16 of converter 137correspond to sockets 58D of patch board 58A of combination setting unit58 for setting the digits of combination sequence S,,,.

Assuming start 5,, switch 28 has been actuated, as different ones of thedigit keys are successively actuated and pulses successively applied tobinary counter 130 on line 127, logical 0 pulses will be successivelyprovided to outputs 1, 2, 3, 4, 5, 6, 7 and 8 of the converter 137.Similarly, assuming start S,,, key 29 is actuated, successive actuationof digit keys producing successive negative pulses input to the binarycounter 130 on line 127 will produce successive logical signals atterminals 9, 10, 11, 12, 13, 14, 15 and 16 of the converter 137.Depending upon the particular digits of digit sequences S,, and S,,,established by the jumper cable connections of patch boards 56A and 58A,the logical O pulses successively produced at terminals 1, 2, 3, 15, 16of converter circuit 137 in synchronism with the successive actuation ofthe digit keys following actuation of start S,, and S,,, switches 28 and19 will be input to the Exclusive-Or gates 100-0, 100-1, 100-9 of thecomparator 100 in digit sequences corresponding to the digit sequencesS,, and S,,,.

Assuming sequence S,, is -2-3-9-4-7-6-3 and further that start S,, 28was actuated, successive entry of any eight digits via the digit keyswill result in the successive application of logical 0 signals fromterminals 1, 2, 3, 4, 5, 6, 7 and 8 of converter 137 to the invertersassociated with Exclusive-Or gates 100-5, 100-2, 100-3, 100-9, l0O-4,100-7, 100-6 and 100-3, respectively. Similarly, assuming the digits ofsequence S,,, are 2-6-5-4-9-8-6-0, and further that start S,,, switch 29was actuated, successive entry of any eight digits via the digit keyswill result in the successive application of logical 0 pulses fromterminals 9, 10, 11, l2, 13, 14, and 16 of the converter 137 to theinverters associated with Exclusive-Or gates 100-2, 100-6, 100-5, 100-4,100-9, 100-8, 100-6 and 100-0. If the digit keys corresponding to thecorrect digits of sequences S,, and S,,, are entered in the correctorder following actuation of the start S,, and start S,,, switches 28and 29, respectively, the successive application of logical 0 signalsfrom terminals 1, 2, 16 of the converter 137 will, in combination withsuccessive entry of the correct digits in the proper order of sequencesS,, and S,,,, result in production of a sequence of logical l signalssuccessive by Exclusive-Or circuits 100-0, 100-1, 100-9 for eachsequence S,, and S,,,.

The incorrect digit detector circuit 112 includes two NAND-digits 146and 147 which have their different inputs respectively connected todifferent ones of the outputs of comparator Exclusive-Or gates 100-0,lOO-l, lOO-9. The outputs of NAND-gates 146 and 147 are input to aNOR-gate 148, the output of which in turn is input to an inverter 149.NAND-gate 146 and 147 in combination with NOR-gate 148 effectivelymonitor the outputs of all of the Exclusive-or gates of the comparator100 to detect entry of an incorrect digit during entry of digitsequences S,, and S,,,. As it will be recalled, if during the entry ofany digit of the sequences S,, and S,,,, the correct digit key and onlythe correct digit key is actuated, logical l signals will be output fromll of the comparator Exclusive-or circuits 100-0, 100-1, 100-9. Ifduring entry ofa digit of sequences S,, and S,,, a digit keycorresponding to an incorrect digit is actuated and/or the digit keycorresponding to the correct digit key is not actuated, all outputs ofthe comparator Exclusive-Or circuits 100-0, 100-1, l0O-9 will not be ata logical 1 level and the output of NOR-gate 148 will be at a logical 0level reflecting the fact that an incorrect key was actuated and- /orthat the correct key was not actuated.

If a logical O is output from NOR-gate 148 at any time during the entryof digit sequence S,, or digit sequence S,,,, an incorrect number latch150 will be set providing a logical 1 signal level on latch output line152. For example, if a logical 0 is output from NOR- gate 148corresponding to either actuation of an incorrect key or failure toactuate the correct key, a logical 1 will be input to the wrong numberlatch from the inverter 149 coincident with the pressure of a pulse online 126, which latter pulse enables the latch 150 to be switched inresponse to the presence of a logical l signal input thereto frominverter 149. With the incorrect digit latch 150 set, a logical 1 signalis present on line 152 which is a manner described hereafter is sampledfollowing entry of the last digit of sequence 5,, and the last digit ofsequence S,,, to determine if one or more incorrect digits or failuresto enter correct digits occurred during entry of sequences S,, and S,,,.Incorrect digit latch 150 is reset by a signal on line 154 each timeeither the start S,, switch 28 or the start S,,, switch 29 is actuatedprior to entry of the digits of sequence S,, or sequence S,,,. Thisenables the wrong digit latch 150 to be independently responsive to theentry of an incorrect digit or the failure to enter a correct digitduring entry of digit sequence S,, and entry of the digits of sequenceS,,,.

The reset signal on line 154 which, as indicated, resets incorrect digitlatch 150 prior to entry of sequence S,, in response to actuation ofstart S,, switch 28 and prior to entry of sequence S,,, in response toactuation of start S,,, switch 29, is produced by a reset circuit 160.Reset circuit 160, in addition to including OR circuit equivalent 140,141 and OR circuit equivalent 142, 143, also includes a single shotcircuit or monostable multivibrator 156 which is responsive to theoutput of a NAND-gate 157, which functions as a logical OR- gate, whichin turn is responsive to the outputs of the start S,, switch 28 andstart S,,, switch 29. Each time either start S,, switch 28 or start S,,,switch 29 is momentarily actuated prior to entry of the digits ofsequences S,, and S,,,, a signal is input to NAND-gate 157 which in turntriggers one shot 156, providing an output line 154 a negative resetpulse which, among other things, resets wrong digit latch 150. Thus,wrong digit latch 150 is reset prior to entry of the digits of sequenceS,, and again prior to entry of the digits of sequence S,,,

To determine whether during the entry of digit sequences S,,and S,,, anincorrect was entered or one of the correct digits not entered, acorrect sequence circuit 159 is provided. The correct sequence circuit159 includes a correct S,, latch 162 and a correct S,,, latch 161.Correct S,, latch 162 and correct S,,, latch 161 are reset in responseto actuation of the start S,, and S,,, switches, respectively.

Correct S,,, latch 161 is also responsive to the output on line 152 ofthe incorrect number latch 150 via NOR- gates 165 and 166, and to theoutput line 131A of the binary counter on which a logical 0 level ispresent when counter 130 has a count of 16 occuring after entry of thelast digit of sequence S,,, and on which a logical 1 signal appears whenbinary counter 130 has a count of 8 which occurs following entry of thelast digit of sequence S,,,. If upon conclusion of entry of the eightdigits of sequence S,,,, the wrong number latch has not been set inresponse to either entry of an incorrect digit or the failure to enter acorrect digit, the correct m latch 161 will be switched when the inputon line 131A is at a logical 0. Under these conditions, the correct mlatch 161 will provide on its output line 163 a logical 0 levelindicating that the correct digits and only the correct digits ofsequence S,,, were entered and that such were entered in the correctorder. This signal on line 163 will illuminate lamp 31 providing avisual indication that sequence S,,, was correctly entered. If, however,during entry of sequence S,,, the wrong number latch 150 is set as aconsequence of either actuation of an incorrect digit key or the failureto operate a correct digit key, correct in latch 161 will not beswitched following entry to the eighth digit of sequence S,,,, providinga logical 1 signal on output line 163. Lamp 31 will not becomeilluminated.

Correct n latch 162 is responsive to the output on line 152 of the wrongnumber latch 150 via NOR-gate 165 and NOR-gate 169, as well as to theoutput of counter line 131A via an inverter 170. Assuming wrong numberlatch 150 has not been set during entry of sequence S,, by eitheractuation of an incorrect key or the failure to actuate a correct key, alogical will be input to latch 162 on line 171 and a logical 0 will beinput on line 172 upon conclusion of the entry of the eighth digit ofsequence 5,, with the result that latch 162 will be switched providing alogical O on latch output line 173. The logical 0 output on line 173illuminates lamp 30 indicating that the sequence 5,, was correctlyentered. If, however, during the entry of sequence 5,, either anincorrect key was actuated or a correct key not actuated, a logical 1signal will be input to the latch 162 from the wrong number latch 150 online 171, and upon occurrence of the logical 0 signal on line 172 uponentry of the eighth digit sequence S,,, correct 11 latch 162 will not beswitched providing a logical l on its output line 173.

Assuming both sequences 5,, and S, have been correctly entered, logical0 level signals will be present on lines 163 and 173. These logical 0level signals on lines 163 and 173, in addition to illuminating bothlamps 30 and 31, are also input to a NOR-gate 175, providing a logical 1signal on the output line 175a from this gate. Thus, if both sequences5,, and S,,, have been correctly entered, a logical l signal will beoutput from NOR- gate 175 on line 175a.

additionally, these NOR-gates prevent clearing of the correct it andcorrect In latches 162 and 161 should any key, except the start 8,, key28 or the start 5,, key 29 be actuated. Stated differently, NOR-gates165, 166 and 169 cause latches 161 and 162 to remain in states they maybe in as a consequence of the fact that sequence S,, or sequence S wascorrectly entered, notwithstanding actuation of a key other than the S,,and S,,, keys 28 and 29.

The digital alarm clock 179 includes a 24hours clock 180 and a daycounter 181 which cooperate to provide a logical 0 level signal on line182 at a specified time of day present in the lock 180 of a specific daysubsequent to setting of the day counter, which day counter settingtypically occurs at the end of a business day prior to closure of thevault door. The logical O signal on line 182 persists until the daycounter 181 is reset to a nonzero count in a manner to be describedlater. For example, and in a manner also to be de scribed, the 24-hourclock 180 and the day counter 181 can be set to provide a signalstarting at 8:00 AM. on the Monday following the close of business thepreceding Friday. Alternatively, the 24-hour clock 180 and the daycounter 181 can be set to provide a logical 0 signal on output line 182starting later the same day and the day counter is set or starting atsome specific time during the next day, 2 days hence, 3 days hence, etc.The logical 0 signal on output line 182 produced starting at the time ofday present in Z4-hour clock 180 on the specified day preset in daycounter 181, in combination with the logical 1 signal on output line aproduced when both the correct 8,. (or S,,') and S,,, (or S,,,)sequences have been entered, are input to the bolt actuator circuit 200,and function to energize solenoids 44A and 44B and permit opening of thevault door, in a manner to be described.

The 24-hour clock is a conventional commercially available digital alarmcircuit such as described in Mostek Corporation Product DescriptionBulletin MK-SOI'IAA/AN, incorporated herein by reference. The 24-hourclock 180 provides on its output lines 180A and 180B signalscontinuously correlated to the correct time of the day in hours, minutesand seconds, or alternatively the time preset therein, in hours, minutesand seconds, when an alarm tone will be produced on clock output line184. The signals on clock output lines 180A and 180B are input to a sixdigit display 52. Each digit of the display 52, of which only one isshown, is of the well-known seven-segment display type. The outputs fromthe 24-hour clock 180 on lines 180A and 1808 are pre-coded such that theseven light-emitting diode segments 52A of each digit display willcooperate to visually display its respective digit. Display 52 includestwo digits to represent the twentyfour possible houts in a day, twodigits to represent the sixth possible minutes in each hour, and twodigits to represent the 60 seconds in each minute. As noted, only onesuch seven-segment digit display is shown, the seven-segment displaysfor the other five digits being identical. Normally, the 24-hour clockdisplay 52 displays the correct time of day. However, if a switch 187,which is normally open, is closed the six-digit display 52 will displaythe time of day preset in clock 180 when a tone signal on line 184 willbe produced.

To set the 24-hour clock 180 to the correct time of day, normally openswitches 188 are closed. This advances the time of day setting of theclock 180. By visually observing the advancing time of day on thedigital display 52 and selectively opening the switches 188 when thedisplayed time in hours, minutes and seconds corresponds to the correcttime of day, the 24-hour clock 180 can be set to the correct time ofday. Further, the preset time of day when the 24-hour clock 180 providesa tone on line 184 can be set as desired by closing both the switch 187and the hour, minute and second switches 188. Closure of switch 187causes the 24-hour clock display 52 to display the time presently presetin the 24-hour clock when the tone would be produced on line 184, whileclosing of switches 188 enables the preset time setting for productionof the tone on line 184 to be advanced. By visually observing the presettone time setting on display 52 and selectively closing the second,minute and hour switches 188 when the displayed tone time matches thatdesired, it is possible to set the 24-hour clock such that the tone online 184 is produced at any desired time of day.

The 24-hour clock 180 preferably includes two counters, namely, a timeof day counter and a tone time counter. The time of day counter isresponsive to a 601-12 reference signal on input line 189 derived from aconventional ac power source and continuously counts 60Hz signals,providing at the output of the time of day counter a signal correlatedto the correct time .of day. This counter is initially set to thecorrect time via switches 188 in the manner described. The tone timecounter is responsive to thhe 60Hz reference signals on line 189 onlywhen it is being set to a specified tone time in response to the jointactuation of switches 187 and 188. Once the tone time counter is set toa specified time of day when a tone signal on line 184 is desired, thiscounter no longer responds to 60Hz signals. When the continuouslyvarying count in the time of day counter correlated to the correct timeof day matches the preset count in the tone time counter correlated to apresent time when a tone is desired, a tone signal on line 184 isproduced, indicating that the current time of day matches the presettime of day when the tone is desired. By providing appropriate codingcircuitry between the output of the time of day counter and the digitaldisplay 52 and between the output of the tone time counter and thedigital display 52, the continuously varying count of the time of daycounter correlated to the correct time of day can be displayed on thedisplay 52, as well as the preset count of tone time counter correlatedto the present time when the tone is desired, depending upon theposition of switch 187.

The 24-hour clock 180, assuming it is set to provide a tone signal online 184 at a preset time of day, such as 8:00 A.M., will provide a tonesignal on line 184 every twenty-four hours at the preset time, that is,each day at 8:00 A.M. To produce a signal at a specified time of day ofa specified day following setting of digital clock 179, such as at 8:00A.M. Monday following setting of the clock thr preceding Friday at theclose of business, a day counter 18] is provided. The day counter 181takes the form of a conventional binary counter, and is connected to thetone signal output line [84 of the 24-hour clock 180 via a normallyclosed switch contact 190 and a single shot circuit 191. Assuming theswitch 190 is in the position shown, each time the logical 1 tone signalis provided on line 184 at the preset time each day, the single shot 191is triggered to provide a logical 1 signal to the day counter 181.Assuming the time signal on line 182 is desired on the third dayfollowing the setting of the clock 179, the day counter 181 would bepreset to a count of 3. As each day passes, a tone signal is provided onoutput line 184 of the 24-hour clock at the second, minute and hour tonetime preset into the 24-hour clock. These signals on line 184 occurringat the preset tone time each day are input via the single shot 191 tothe day counter 181 decrementing the day counter. When the day counter181 decrements to a count of O, the logical 0 signal on line 182 isprovided indicating that the time of day is equivalent to the specifiedtone time preset in the 24-hour clock and further that the specifiednumber of days preset in the day counter 181 have elapsed since thesetting of the day counter 181. The logical 0 signal on line 182 remainsuntil day counter 181 is reset to a nonzero count.

For example, if at the close of business on Friday the day counter 181is preset to a count of 3, a signal will be provided on line 182starting with receipt of three tones signals from the 24-hour clock online 184. 1f the 24-hour clock is for 8:00 A.M., the tone signals online 184 will be produced at 8:00 A.M. Saturday, 8:00 A.M. Sunday and8:00 A.M. Monday, each of which will decrement the day counter 181 in asingle count. When the third tone signal on line 184 is produced at 8:00A.M. Monday, the day counter 181 will be decremented to 0 at which timea signal will be produced on line 182 indicating that it is 8:00 A.M.Monday. As noted, this signal on line 182 persists until day counter 181is reset to nonzero count. Similarly, if the day counter 181 has beenpreset to counts of2 or 1, a signal would be provided on line 182starting at 8:00 A.M. Sunday or 8:00 A.M. Saturday, respectively.

The output lines 181A of the day counter 181 provide signals in binaryformat indicating the count presently in the day counter. These signalsare input to a decoder 192 which conditions them for controlling asignal digit seven-segment light-emitting diode display 193. The countto which the day counter 181 is preset can be increased or decreased topreset it to a different count. 1f the count currently in the daycounter 181 is to be decreased, switch 194 is placed in the positionshown and switch is transferred from the position shown. The count nowdecreases and when the decreasing count in the day counter 181 asdisplayed by the display 193 reaches that desired, switch 190 istransferred to the position shown. Similarly, if it is desired toincrease the count to which the day counter 181 is presently preset, theswitch 194 is transferred from the position shown, as is the switch 190.The count now increases and when the increasing count in the day counter181 as displayed in the display 193 reaches that desired, the switch 190is transferred to the position shown.

The output of the single shot 191 on line 191A produced each time a tonesignal is provided on line 184 from the 24-hour clock 180 is alsocoupled via a transistor switch 196 to an input line 197 of the 24-hourclock 180, terminating the tone.

In an effort to compromise the system, an unauthorized person mayattempt to accelerate the time at which the signal is produced on line182, for example, from Monday morning at 8:00 A.M. when bank employeesare customarily present in the bank to some earlier time during thepreceding weekend when the bank employees are not likely to be present.To avoid this, a clock speed-up prevention circuit 199 is employed. Thecircuit 199 is connected between the 601-12 reference signal line 189input to the 24-hour clock and a power supply 201 from which the 601-12reference signal is normally derived, the power supply 201 itself beingconnected via a suitable plug 202 to a conventional 60Hz source ofpower. Should the frequency of the signal from the power supply 201input to the clock speed-up prevention circuit 199 on line 198 exceed60Hz to any significant extent, the clock speed-up prevention circuit199 provides on line 189 a continuous logical 1 signal causing the24-hour clock'l80 to switch to an internal 60Hz oscillator for referencepurposes.

The circuit 199 is in the form of a single shot having a period slightlyless than l/60 second. Assuming the frequency of the a.c. signal fromthe power supply 201 input to the clock speed-up prevention circuit 200on line 198 is approximately 601-12, the one shot 199 will be triggeredto provide logical 1 signal pulses on line 189 to the 24-hour clock 180at a 601-12 rate. Since the duration of logical l pulse output from theone shot is less than 1/60 of a second, the output of the clock speed-upprevention circuit 199 on line 189 will drop to zero at the end of eachone-shot pulse. but prior to the next 60Hz triggering signal from thepower supply 201. When the output line of the circuit 199 drops to alogical O. which occurs at a 60Hz rate assuming the ac. frequency fromthe power supply 201 input to the circuit 199 is at 60112. a capacitor205 which has been charging through a resistor 206 during the durationof the logical 1 single shot output from the circuit 199, will dischargethrough diode 207. However, should the frequency input to the 24-hourclock 180 via the circuit 199 be substantially above 60Hz. the output online 189 of the single shot of circuit 199 remains at a logical l,preventing capacitor 205 from discharging. As a result of the continuedlogical 1 level on line 189 to the 24-hour clock 180, this clockswitches to an internal 60Hz reference signal source contained withinthe clock.

FIG. 6 depicts one possible form of circuit, which can be incorporatedin 24-hour clock 180, for switching to an internal source of referencesignals for advancing the 24-hour clock 180 should an attempt be made tospeed up the 24-hour clock by connecting to it an external source ofreference signals having a frequency sugstantially greater than thatnormally provided by the power supply 201, which typically would be60Hz. The circuit includes a single shot 320 responsive to the signalinput on line 189, a 60Hz free-running oscillator 321 which functions asan internal source of 601-12 signals, and NAND-gate 322 which isresponsive to the output of the single shot 320 on line 323 and theoscillator output on line 324.

As noted previously, if the source of reference pulses input to theclock speed-up prevention circuit 199 on line 273 substantially exceedsthe desired reference Signal frequency, for example 60Hz. the speed-upprevention circuit 199 provides on its outut 189 a logical l signallevel, the signal on line 189 normally being in the form of 60Hz pulsesif the reference signals on line 273 are normal. Assuming that at time Ithe signal on line 189 switches from pulses to a logical 1 level inresponse to a change in frequency of the reference signals on line 27360Hz to an excessive frequency, the single shot 320 is triggered at timet providing a logical pulse on single shot output line 323. The pulseoutput from the single shot 320 on line 323 starts at time correspondingto the point when the frequency of reference signals on line 189 becameexcessive and continues in time until time 1 when the single shot 320times out. Assuming the single shot 320 still has a logical 1 signalinput to it on line 189 due to the fact that the reference signalfrequency on line 273 remains excessive, when the output from the singleshot on line 323 reverts to a logical level at time 1,, NAND-gate 322 isenabled, gating 60Hz signals from free-running internal reference signaloscillator 321 to NAND-gate output line 325. The 60Hz reference signalson line 325 gated from the internal reference signal oscillator 321continue until such time as the frequency of the reference signals fromthe external source on line 273 drop to an acceptable level whereuponthe signal on line 189 reverts to a logical 0. The 60Hz output on line325 present when the frequency of timing signals on line 273 isexcessive advances the clock 180 in the same manner as the pulses online 273 do when the frequency of reference signals on line 273 is notexcessive.

The bolt actuator circuit 200, which includes solenoids 44A and 44B, isprovided to raise the detent 42 and thereby disengage it from the boltnotch 40, allowing the vault door to be opened by turning the handle 23,when both combination sequences 5,, (or S,,') and S,,, (or S,,,) havebeen properly entered at or after the predetermined time preset in the24-hour clock 180 of the specified day preset in day counter 181. Thebolt actuator 200 is responsive to output line A of NOR- gate 175 which,as previously indicated. provides a logical 1 signal when both sequences5,, (or 5") and S,,, (or S,,,) have been properly entered. The boltactuator circuit 200 is also responsive to output line 182 of the daycounter 181 on which there is a logical 0 signal at or after thespecified time of day preset in alarm clock of the specified day presetin the day counter 181. The logical 1 level signal input to the boltactuator circuit 200 on line 175A reflecting the fact that bothsequences S (or S,,) and S,,, (or S,,, have been correctly entered isresistor coupled to two parallel-connected transistor switches 203 and204 in the form of Darlington circuits, each of which .is connected inseries with a different one of the solenoids 44A and 44B which, whenenergized, raise the detent 42 to disengage it from the bolt notch 40.The logical 0 signal input to the bolt actuator circuit 200 from the daycounter 181 on line 182 produced at and after the time preset in 24-hour clock 180 of the day preset in counter 181, following inversion ina transistor 195, is input to two parallel-connected transistor switches208 and 209, also Darlington circuits. Transistor switches 208 and 209are connected in series with different ones of the solenoids 44A and 44Band different ones of the transistor switches 203 and 204 responsive tothe signal on line 175A from the correct 5,, (S,,') and S,,, (or S,,,)NOR-gate 175. Assuming the correct sequences 5,, (S,,) and S,,, (orS,,,) have been entered at or after the specified time preset in the 240hour clock 180 on the specified day preset in the day counter 181, thelogical 1 and logical O signals input to the bolt actuator circuit 200on lines 175A and 182, respectively, will switch the Darlington circuittransistor switches 203, 204 and 208, 209 to a conductive state,energizing solenoids 44A and 44B. With these solenoids energized, thebolt detent 42 is raised disengaging the bolt notch 40, allowing thebolt 22 to be moved to its unlocked position by rotation of the handle23 in a manner previously described. While both of the solenoids 44A and448 will normally be energized in response to logical O and logical lsignals input to the bolt actuator circuit 200 on lines 182 and 175A,respectively, energization of either one of the solenoids 44A and 44Bwill be sufficient to raise the detent 42 to disengage it from the boltnotch 40. The inclusion of two solenoids 44A and 448 in parallel ismerely to provide a factor of safety should one solenoid becomedefective.

A duress circuit 210 is provided to permit rmote signaling to a policestation or the like should the bank employees be required, under threatof force, to open the vault. Specifically, the duress circuit 210permits the vault door 19 to be opened while at the same time an alarmsignal sent to a remote police station or the like should both duresssequences 8,, and S,,, be entered at or after the time of day preset inthe 24-hour clock 180 on the specified day preset in the day counter181. As it will be recalled, duress sequences 5,, and S,,, are identicalto the normal sequences 8,, and S,,,, except that the last or eighthdigit of each sequence is changed. Specifically, and by way of exampleonly, the duress sequence 8,, is -2-3-9-4-7-6-0 instead of5-2-3-9-4-7-6-3, while the duress sequence Sm is 2-6-5-4-9-8-6-8 insteadof 2-6-5-4-9-8-6-0. Obviously, more than one digit could be changed tomodify the normal sequence to produce the duress sequence, oralternatively digits could be added to or removed from the normalsequence to produce a duress sequence.

The duress circuit 210 includes a NOR-gate 211 and an inverter 212, theNOR-gate being responsive to the count seven output of thebinary-to-decimal converter 137 and the zero digit key 26-0 of thekeyboard 26. Should a zero be entered into the keyboard 26 by depressingkey 26-0 as the eighth digit of a sequence 8,, following actuation ofthe start S,, key 28, a logical 0 signal will be input to both inputs ofthe NOR-gate 211 providing at the output 213 of inverter 212 a logical 0signal. The logical 0 signal on line 213 is input via separate diodes tothe inverter associated with the Exclusive-Or gate 100-0 of thedepressed digit key 26-0, and the input line of Exclusive-Or gate 100-3associated with digit key 26-3 which would normally have been actuatedas the eighth digit sequence S,, had the duress key 26-0 not beactuated. The input to Exclusive-Or gate 100-0 cancels, insofar as theincorrect digit detector circuit 112 is concerned, the fact that duresskey 26-0 has been actuated as the eighth digit of the sequence S,,'. Aswill be recalled, the eighth digit of the normal sequence 5,, is a 3 inthe example herein, and under normal conditions actuation of the 0 digitkey 26-0 following depression of start S,, key 28 as the eighth digit ofa sequence instead of the digit key 26-3 will produce a logical 0 outputfrom the Exclusive-Or gate 100-0 which when input to the incorrect digitcircuit 112 will result in setting the incorrect number latch 150. Byfeeding the output of NOR-gate 211 following inversion in inverter 212to Exclusive-Or gate 100-0, the output of Exclusive-Or gate 100-0associated with duress key 16-0 will provide a logical 1 output to theincorrect digit detector circuit during entry of the eighth digit ofduress sequence S,, in much the same fashion as would have occurred hadthe normally correct eighth digit key 26-3 of sequence 8,, been enteredand the duress key 26-0 of sequence 5,, not actuated.

The inverted output of duress NOR-gate 211 is also input to Exclusive-Orgate 100-3 associated with digit key 26-3 which is the correct eighthdigit for the normal sequence S,,. the input to Exclusive-Or gate 100-3simulates the actuation during entry of the eighth digit of the duresssequence 5,, of the correct eighth digit of the normal sequence S,,. Asa consequence, Exclusive- Or gate 100-3 provides a logical l at itsoutput as would normally occur were the correct digit, a 3 in theexample assumed herein, had been entered as the eighth digit of thesequence S,, This logical 1 signal from Exclusive-Or gate 100 100-3 isinput to the incorrect digit detector circuit 112 preventing the wrongnumber latch 150 from being set even though the correct digit key 26-3associated with normal sequence S, had not been actuated. Thus, duressNOR-gate 211 and associated inverter 212, insofar as concerns theincorrect digit detector circuit 112, simulates actuation of the correctdigit key of the normal sequence 8,, and overrides the actuation of theduress key 26-0 which, while correct for the duress sequence S,,, isincorrect for the normal sequence S,,.

A NOR-gate 214 and inverter 215 function in a similar manner withrespect to the duress sequence 8,, as NOR-gate 211 and inverter 212function with respect to the duress sequence S,,. NOR-gate 214 isresponsive to the count 15 terminal of the binary-to-decimal converter137 and to the duress key 26-8 associated with the last digit of duresssequence S,,,' to provide on inverter output line 216 a logical 0 signalwhen the duress digit 8 is actuated as the eighth digit of the duresssequence. Sm instead of the normal digit 0 constituting the last digitof the normal sequence S,,,. The output line 216 of inverter 215 isinput to Exclusive-Or gate -8 associated with the duress key 25-8 toeffectively override, insofar as incorrect digit detector circuit 112 isconcerned, the fact that the digit key 8 was actuated as the eighthdigit of the sequence S,,,', preventing latch from being set. The outputinverter 215 on line 216 is also input to Exclusive-Or gate 100-0 toeffectively simulate the actuation of digit key 26-0 which correspondsto the last digit of the normal sequence S,,,, thereby preventing theincorrect digit detector circuit 112 from setting latch 150 as aconsequence of the actuation of duress key 26-8 rather than digit key26-0 as the last digit of the sequence S,,,.

The outputs 211A, 214A of the duress NOR-gates 211 and 214 are input toa NOR-gate 220, the output of which is input to a latch 221. Shouldeither the duress key 26-0 be entered as the last digit of the duresssequence 8,, or the duress digit 26-8 be entered as the last digit ofthe duress sequence S,,,', a logical 0 output is provided from NOR-gate220 to latch 221 setting this latch. Setting of latch 221 in turnprovides a logical 1 signal on latch output line 70. The duress signalon line 70 is input, via contact 63 which is in the position shown whenthe bolt 22 is in the lock position, to a remote station, such as thepolice, connected to line 71. Thus, when at least the last of twosequences entered is a duress sequence, either 5,, or S,,,', and suchsequences are entered at or after the specified time preset in the24-hour clock during the specified day preset in the day counter 181,not only are the bolt solenoids 44A and 44B energized to permit the boltto be moved to its unlock position, but a signal is provided to a remotestation, such as the police, to reflect the fact that the vault door isbeing opened under duress conditions.

To reset the various latch circuits such as the correct n latch 162,correct in latch 161, incorrect digit detector latch 150, and duresslatch 221 a start power reset circuit is included. The circuit 185includes a transistor switch 186, the base of which is coupled via aresistor 217 and a capacitor 218 to a source of positive potential 219,which potential source 219 is included in power supply 201 to bedescribed and is energized only when the power supply 201 is in an ONcondition by reason of switch 183 being closed-circuited. The emitter oftransistor 216 is coupled to the output of the start 5,, switch 28 andthe output of the start S,,, switch 29. When power supply 201 is turnedON by closure of a power ON switch 183 to be described, the power supply219 is energized providing bias to the base of transistor 216 to placethis transistor in a conductive state. Conduction of transistor 216brings the emitter thereof to ground potential with the result that alogical 0 or lower level signal is applied to the output of start 8,,

switch 28 and start S,,, switch 29. These signals in turn reset correctn latch 162 and correct m latch 161 and via the reset circuit 160 resetsthe wrong number 150 and the duress latch 221. Following charging of thecapacitor 218, transitor 216 is switched to a nonconductive stateterminating the reset signals applied from the emitter of transistor 216to the output line of start 8,, switch 28 and start S,,, switch 29.

The start power reset circuit 185 is also responsive to a boltretraction reset circuit 167. When the bolt 22 is switched from its lockposition to its unlock position, movable contact 68 switches from theposition shown in which capacitor 72 is charging from a source ofpositive potential 73 to a position in which contacts 65 and 66 areelectrically connected. This enables the charged capacitor 72 todischarge through a resistor 222 via line 74. This causes the transistor186 to be temporarily switched to a conductive state. Conduction oftransistor 186 resets the correct It latch 162, correct In latch 16,duress latch 221, and the wrong number latch 150 in the same mannerdescribed in connection with the initial energization of power supply201 by the closure of normally open switch 183. When the capacitor 72had fully discharged, transistor switch 186 is again renderednon-conductive to terminate the reset function. Thus, by virtue of thebolt retraction reset circuit 167 which, via circuit 185 and resetcircuit 160, resets the latches 150, 221, 161 and 162 when the bolt isplaced in its unlock or open condition, the control circuit isautomatically reset each time the vault door is opened, requiring, oncethe door has been closed, and before it can be again opened, that thesequences 5,, (or S,,') and S,,, (or S,,,) be entered at or after thespecified time preset in the 24-hour clock 180 of the specified daypreset in the day counter 181.

To facilitate energization of one or both of the solenoids 56F and 58Fto permit access to the patch board 56A and 58A of the combinationsetting units 56 and 58, a combination setting access circuit 230 isprovided. As it wil be recalled, access to one or the other or both ofthe combination setting units 56 and 58 is possible by entering one orthe other or both of the duress sequences 8,, and/or S,,, following a)entry of both normal sequences 8,, and S,,, at or after the specifiedtime preset into the 24-hour clock 180 during the specified day presetin the day counter 181 and b) retraction of hot] 22. Access tocombination change units 56 and/or 58 can also be obtained if, beforeretracting bolt 22 and opening the door, the duress sequences 5,, andS,,, are entered instead of the normal sequences 8,, and m- When bothsequence 5,, (or and sequence S,,, (or S,,,) are entered and the bolt 22placed in its retracted position to permit access to the rear door 19,movable contact 63 is transferred from the position shown such that itelectrically connects stationary contacts 60 and 61. when one or theother of the duress sequences 5,, or S,,,, or both, are enteredfollowing retraction of the bolt 22 to the open position and transfer ofthe contact 63 from the position shown, the duress signal on line 70provided by the duress latch 221, which has been set in the mannerpreviously described as a consequence of entry of one or the other orboth of the duress sequences 5,, or S,,,, is applied to line 75. Theduress signal on line 75 switches a normally nonconductive Darlingtontransistor switch 177 to its conductive state, applying a logical 0level signal to line 223. The logical 0 signal on line 223 is effectiveto ground the emitters of transistor switches 224 and 225 which arenormally nonconducting. If the correct duress sequence S,, is entered.the logical 0 level output on line 173 from the correct n latch 162 isinput to the base of a transistor switch 226 placing this normallynonconducting switch in a conductive state. Similarly, if the correctduress sequence S,,, is entered, the logical 0 level signal output online 163 from the correct m latch 161 is input to the base ofa normallynonconducting switch 227 rendering this transistor conductive. With theemitters of transistors 225 and 224 at ground potential as a consequenceof line 223 being grounded due to application of the duress signal linevia the bolt-controlled, transferred contact 63, a logical 0 signalinput to transistor 226 switches transistor 225 to a conductive stateenergizing solenoid 56F permitting access to combination changing unit56, while a logical 0 input to the base of transistor 227 reflectingcorrect entry of the duress sequence S,,, switches transistor switch 224to a conductive state energizing solenoid 58F to permit access to thecombination changing unit 58. If logical 0 signals are simultaneouslyinput to transistor 226 and 227 indicating that both the correct duresssequence 5,, and correct duress sequences S,,, have been enteredfollowing retraction of bolt 22, both solenoids 56F and 58F will beenergized to permit access to both combination setting units 56 and 58.

The power supply 201 includes an input plug 220 which is normallyconnected to a conventional l lvolt/6OHZ power source. The switch 183permits the available power input at plug 202 to be applied to the cicuit 201 as desired. A transformer 270 and full wave rectifier 271provide on line 272 24-volt full-wave rectified dc. power which is usedto energize various of the solenoids 44A and 44B, 56F and 58F. One sideof the transformer secondary winding is connected via line 273 and aclipping circuit 274 to the input of the clock speed-up preventioncircuit 199 to provide a 60Hz reference signal to the 24-hour clock in amanner previously described. The center tap terminal of the transformersecondary winding is at approximately 12 volts for application ofenergizing potential to the 24-hour clock display 52 via line 270A.Additionally, the center tapped potential of the secondary winding oftransformer 207 is applied to a regulator circuit 275 which is at itsoutput 276 provides a regulated 5-volt d.c. potential for energizing theday counter 181. The center tapped potential of secondary winding oftransformer 270 is also applied to l2-volt d.c. regulator circuit 280for providing regulated l2-volt power to the 24-hour clock 180.

The center tapped voltage output from secondary winding of transformer270 is further input via a charging resistor 277 to a stand-by battery278.

Normally, the 24-hour clock 180 and the day counter 181 are energizedfrom regulated supplies 275 and 280 of appropriate potentials present onlines 276 and 280A which derive their power from an external supply viaplug 202. Should, however, the external supply to which plug 202 isconnected fail, the day counter 181 and the 24-hour clock 180 will beenergized by the stand-by battery 278.

The remaining logic circuit components of the control circuit of FIGS.4A and 4B are normally energized from a suitably regulated 5-volt d.c.supply 282A taken at line 282 which in turn is derived from power froman external source via plug 202. Should the external source to whichplug 202 is connected fail, these remaining logic circuit componentswill be de-energized. Further. should the external power supply to whichplug 202 is connected fail, the various solenoids 44A, 44B, 56F, 58F,which are normally energized via the full-wave rectifier 271 output online 272, will become de-energized. Additionally, the 24-hour clockdisplay 52 normally energized from the center tap of the secondarywinding of transformer 270 wil cease to be energized if the externalsource to which plug 202 is connected fails. Thus, all circuitcomponents, with the exception of the clock 180 and day counter 181energized from lines 280A and 276 by a stand-by battery 278, will ceaseto be energized as a consequence of a failure of power at plug 202.

As noted, should the power supply to which the plug 202 is connectedfail, the 24-hour clock 180 and the day counter 181 will continue to beadvanced by the stand-by battery 278. However, all remaining logiccircuitry as well as the solenoids will be without electrical power. Toenable these unpowered circuit components and solenoids to be poweredfrom outside of the vault to facilitate opening of the vault at thepredetermined hour preset in the 24-hour clock 180 on the predeterminedday preset in the day counter 181, the 24volt line 272 and the centertap 270A of the secondary winding of transformer 270 are connected tosockets 285 and 286 which are accessible from the exterior of the vaultas, for example, by flush-mounting the sockets in the exterior surfaceof the vault 10. With sockets 28S and 286 accessible from the exteriorof the vault 10, an auxiliary power supply (not shown) could beconnected thereto to provide power to lines 270A and 272 from theexterior of the vault, thereby enabling the vault door to be opened uponproper entry of sequences S,, (or S,, and S,,, (or S,,,) when the24-hour clock 180 and day counter 181 are advanced to their respectivepreset time and day settings under the power provided by stand-by source278, notwithstanding a failure of the external supply connected to theplug 202.

Should a person inadvertently become locked in the vault, a normallyopen switch 288 connected between the base of transistor 195 and groundpotential is provided, which is accessible from the interior of thevault.

Closure of switch 288 applies a logical 0 level signal to input line 182of the bolt actuator circuit 200 to simulate the condition produced whenboth the 24-hour clock 180 has arrived at the predetermined time presenttherein and the day counter has arrived at the predetermined day presetin it with a logical O signals present on line 182 as a consequence ofclosure of normally open switch 288 by the person locked in the vault10, to unlock the vault dooe by energization of the solenoids 44A and448 it is only necessary to enter the correct combinations 5,, (or S,,')and S,,, (or S,,,) using the keyboard 26. Thus, if a person isinadvertently locked in the vault, the vault door can be opened,assuming switch 288 is closed, by proper entry of the combinationsequences S, (or S,,') and S,,, (or S,,,) in keyboard 26 without waitinguntil the 24-hour clock 180 and day counter 181 arrive at the time ofday and day settings preset therein.

In lieu of providing ten separate digit keys 26-0, 26-1, 26-9 for eachof the ten digits 0, l, 9, the single digit key keyboard shown in FIG. 3and the circuit depicted in FIG. 5 may be provided. This keyboard andcircuit includes a single digit display 300 which at any given timedisplays a single one of the digits 0, 1, 9. The particular digit beingdisplayed in display 300 can be changed at will by actuation of anadvance digit switch 301. Entry into the system of the digit displayedin the display 300 is accomplished by momentary actuation of an enterdigit switch 302. To enter the multiple digits of a sequence S,,, S,,',S,,,, or S,,,, the advance switch 301 is successively utilized tosuccessively cause the single digit display 300 to display thesuccessive digits of the particular digit sequence being entered. Whenthe display 300 contains a digit it is desired to enter, the digit enterswitch 302 is actuated. For example, if the normal sequence 5,,consisting of digits 5-2-3-9-4-7-6-3 is to be entered, the advanceswitch 301 is actuated to cause the numeral 5 to be displayed by display300 whereupon the enter digit switch 302 is actuated to enter thisdigit. Thereafter, the advance switch 301 is operated to display numeral2 in the display 300 following which the enter digit switch 302 isactuated to enter the second digit 2 of the sequence. This procedure isrepeated until all eight digits of a sequence have been displayed in thedisplay 300 and the displayed digits entered by the enter digit switch302.

The circuit of FIG. 5 affords a greater degree of security for enteringthe digits of the combination sequences S,,, S,,, S,,, and S,,, than themulti-digit keyboard 26. specifically, with the keyboard 26, an observerattempting to learn the digits of the combination sequences can, byobserving the location of the switches being successively actuated,determine the identity ofthe digits of the sequence. Whereas, with thecircuit of FIG. 5, entry of a digit is accomplished by actuating thesame switch, namely, digit switch 302 while observing a display 300visable only to the person entering the number, which display iscontrolled by the advance switch 301. Hence, it is not possible todetermine the digits being entered by noting the position of theoperators finger as he successively actuates different ones of the digitswitches 26.

The circuit of FIG. 5 includes a binary counter 305 which is connectedto a source of low frequency pulses 306, e.g., 2H2, via a line 307. Thepulse source 304 may be any free-running multilvibrator having arelatively low frequency. The counter 305 is also responsive to thenormally open advance switch 301. When the advance switch 301 is closed,that is, transferred from the normally open position shown, the 21-12clock pulses continuously presenton line 307 are entered into thecounter 305 causing the counter to repeatedly cycle through counts of 0,l, 9, the counting and recycling continuing so long as the switch 301 isclosed. The output of the binary counter 305 on lines 306 at any giventime reflects the counts then stored in the counter 305.

The output of the counter 305 on line 306 is input to the digit display300 which preferably takes the form of a conventional seven-segment LEDdisplay 3l0 via a coding unit 311 which converts the binary signals online 306 indicative of the count in counter 305 into a form suitable forilluminating the seven light-emitting diode segments of the display 310.Thus, the count in counter 305 at any given time is displayed by thedisplay circuit 300 and as the counter 305 cycles in response to the 2H2signals input thereto on line 307 when the advance switch 301 is closed,the display 300

1. An electronic combination lock system for permitting access to persons correctly entering the digits of a predetermined multi-digit combination, comprising: digit entry means for entering multiple digits when access is desired, said digit entry means generating electrical signals correlated to the digits entered, said digit entry means including: a. display means for displaying at a given time only a selected one of a multiplicity of different digits, said display means being sequentially operable to sequentially display different selected digits, b. digit signal generating means for generating electrical signals correlated to the digit displayed by said display means, c. a first actuator means actuatable by a person seeking access for controlling the display of digits in response to said electrical digit signals, and d. a second actuator means actuable by a person seeking access for controlling the entry of a digit into said system to cause digit signals correlated to the displayed digit to be output from said digit entry meAns, said second actuator being actuatable independently of the actuation of said first actuator means, validation means responsive to the electrical signals generated by said data entry means for determining if the digits entered correspond correctly to said predetermined multi-digit combination and generating a first electrical control signal upon correct correspondence, and means responsive to said first electrical control signal for permitting access.
 2. The system of claim 1 wherein said digit signal generating means includes a counter and a pulse source input to said counter for altering the count in said counter, said display means being responsive to the output of said counter for displaying the digit correlated to the count in said counter, said actuator means being operable upon actuation to cause digit signals correlated to the count in said counter when said actuator means is actuated to output from said digit entry means. 